DAC
2012
ACM
12 years 1 months ago
2012
ACM
Spin-Transfer Torque RAM (STT-RAM) is an emerging non-volatile memory (NVM) technology that has the potential to replace the conventional on-chip SRAM caches for designing a more ...
PLDI
2012
ACM
12 years 1 months ago
2012
ACM
While graphics processing units (GPUs) provide low-cost and efficient platforms for accelerating high performance computations, the tedious process of performance tuning required...
PPOPP
2012
ACM
12 years 6 months ago
2012
ACM
This paper introduces a programming interface called PARRAY (or Parallelizing ARRAYs) that supports system-level succinct programming for heterogeneous parallel systems like GPU c...
CSE
2012
IEEE
12 years 6 months ago
2012
IEEE
—Continuum quantum Monte Carlo (QMC) has proved to be an invaluable tool for predicting the properties of matter from fundamental principles. By solving the manybody Schr¨odinge...
ARC
2012
Springer
12 years 6 months ago
2012
Springer
As the size of FPGA devices grows following Moore’s law, it becomes possible to put a complete manycore system onto a single FPGA chip. The centralized memory hierarchy on typica...
HIPEAC
2011
Springer
12 years 10 months ago
2011
Springer
For each computer system generation, there are always applications or workloads for which the main memory size is the major limitation. On the other hand, in many cases, one could...
HIPEAC
2011
Springer
12 years 10 months ago
2011
Springer
In chip multiprocessors (CMPs), data accesslatency dependson the memory hierarchy organization, the on-chip interconnect (NoC), and the running workload. Reducing data access late...
JCPHY
2011
13 years 1 months ago
2011
The calculation of radial distribution functions (RDFs) from molecular dynamics trajectory data is a common and computationally expensive analysis task. The rate limiting step in ...
PE
2010
Springer
13 years 5 months ago
2010
Springer
Accurately characterizing the resource usage of an application at various levels in the memory hierarchy has been a long-standing research problem. Existing characterization studi...
IPPS
2010
IEEE
13 years 8 months ago
2010
IEEE
The memory hierarchy of most multicore systems contains one or more levels of cache that is shared among multiple cores. The shared-cache architecture presents many opportunities f...