Power Dissipation in Deep Submicron CMOS Digital Circuits

— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley Short-Channel IGFET model and fits HSPICE simulation results well. Static and dynamic power analysis for various threshold voltages is addressed. A design methodology to minimize the power-delay product by selecting the lower and upper bounds of the supply and threshold voltages is presented. The effects of the supply voltage, the threshold voltage, and ; which reflects the drain induced barrier lowing, are also addressed.

• Type: Conference
• Year: 1995
• Where: ISCAS
• Authors: R. X. Gu, Mohamed I. Elmasry
• Keywords: Hardware, ISCAS 1995, Simple Analytical Model, Threshold Voltage, Various Threshold Voltages