Time-constrained code compaction for DSPs

{DSP algorithms in most cases are subject to hard real-time constraints. In case of programmable DSP processors, meeting those constraints must be ensured by appropriate code generation techniques. For processors oering instruction-level parallelism, the task of code generation includes code compaction. The exact timing behavior of a DSP program is only known after compaction. Therefore, real-time constraints should be taken into account during the compaction phase. While most known DSP code generators rely on rigid heuristics for that phase, this paper proposes a novel approach to local code compaction based on an Integer Programming model, which obeys exact timing constraints. Due to a general problem formulation, the model also obeys encoding restrictions and possible side eects. 1

• Type: Conference
• Year: 1995
• Where: ISSS
• Authors: Rainer Leupers, Peter Marwedel
• Keywords: Code Compaction, Code Generation, Hardware, ISSS 1995, Real-time Constraints