Power analysis and low-power scheduling techniques for embedded DSP software

This paper describes the application of a measurement based power analysis technique for an embedded DSP processor. An instruction-level power model for the processor has been developed using this technique. Signicant points of dierence have been observed between this model and the ones developed earlier for some general-purpose commercial microprocessors [1, 2]. In particular, the eect of circuit state on the power cost of an instruction stream is more marked in the case of this DSP processor. In addition, the DSP processor has a special architectural feature that allows instructions to be packed into pairs. The energy reduction possible through the use of this feature is studied. The on-chip Booth multiplier on the processor is a major source of energy consumption for DSP programs. A micro-architectural power model for the multiplier is developed and analyzed for further energy minimization. A scheduling algorithm incorporating these new techniques is proposed to reduce the energ...

• Type: Conference
• Year: 1995
• Where: ISSS
• Authors: Mike Tien-Chien Lee, Vivek Tiwari, Sharad Malik, Masahiro Fujita
• Keywords: Dsp Processor, Embedded Dsp Processor, Energy Reductions, Hardware, ISSS 1995