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46

ITC
1995
IEEE

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An Experimental Chip to Evaluate Test Techniques: Experiment Results

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An Experimental Chip to Evaluate Test Techniques: Experiment Results

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This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given.

Siyad C. Ma, Piero Franco, Edward J. McCluskey

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Combinational Circuitry | Hardware | ITC 1995 | Test Conditions | Various Test Techniques |

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Added	26 Aug 2010
Updated	26 Aug 2010
Type	Conference
Year	1995
Where	ITC
Authors	Siyad C. Ma, Piero Franco, Edward J. McCluskey

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