MICRO
2000
IEEE
14 years 6 days ago
2000
IEEE
To exploit increased instruction-level parallelism available in modern processors, we describe the formation and optimization of tracenets, an integrated approach to reducing the ...
PLDI
1995
ACM
14 years 4 months ago
1995
ACM
Traditional list schedulers order instructions based on an optimistic estimate of the load latency imposed by the hardware and therefore cannot respond to variations in memory lat...
MICRO
1995
IEEE
14 years 4 months ago
1995
IEEE
Exploitation ofinstruction-levelparallelism is an ejfective mechanism for improving the performance of modern super-scalar/VLIW processors. Various software techniques can be appl...
ARC
2007
Springer
14 years 4 months ago
2007
Springer
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
SC
1992
ACM
14 years 4 months ago
1992
ACM
Exploiting parallelism at both the multiprocessor level and the instruction level is an e ective means for supercomputers to achieve high-performance. The amount of instruction-le...
HPCN
1998
Springer
14 years 4 months ago
1998
Springer
In this paper, we evaluate two different approaches for the compiler-based parallelisation of a C program for MPEG-2 decoding. The first approach experiments with a commercial auto...
ASPLOS
1998
ACM
14 years 4 months ago
1998
ACM
Advances in VLSI technology will enable chips with over a billion transistors within the next decade. Unfortunately, the centralized-resource architectures of modern microprocesso...
ISCA
1998
IEEE
14 years 4 months ago
1998
IEEE
This paper develops and validates an analytical model for evaluating various types of architectural alternatives for shared-memory systems with processors that aggressively exploi...
HPCA
1998
IEEE
14 years 4 months ago
1998
IEEE
The performance of a concurrent multithreaded architectural model, called superthreading 15 , is studied in this paper. It tries to integrate optimizing compilation techniques and...
ICPP
2005
IEEE
14 years 6 months ago
2005
IEEE
Java-based middleware is a rapidly growing workload for high-end server processors, particularly Chip Multiprocessors (CMP). To help architects design future microprocessors to ru...