The Verification of the On-Chip COMA Cache Coherence Protocol

This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of integrating hundreds to hundreds of thousands of processors on single silicon chip. We use ract State Machine (ASM) as a theoretical framework for the specification of the on-chip COMA cache coherence protocol. We show that the protocol obeys the Location Consistency model proposed by Gao and Sakar.

• Type: Conference
• Year: 2008
• Where: AMAST
• Authors: Thuy Duong Vu, Li Zhang, Chris R. Jesshope
• Keywords: AMAST 2008, Cache Coherence Protocol, COMA Cache Coherence, On-chip Coma Cache, Software Engineering