As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
Andrew DeOrio, Konstantinos Aisopos, Valeria Berta...
—This paper describes the methods used to formulate and validate the memory subsystem of the cache-coherent Sun Scalable emory MultiProcessor (S3.mp) at three levels of abstracti...
Fong Pong, Michael C. Browne, Gunes Aybay, Andreas...
This paper gives a correctness proof for the on-chip COMA cache coherence protocol that supports the Microgrid of microtheaded architecture, a multi-core architecture capable of in...
-- The Express Ring is a new architecture under investigation at the University of Southern California. Its main goal is to demonstrate that a slotted unidirectional ring with very...
We consider the formal verification of the cache coherence protocol of the Stanford FLASH multiprocessor for N processors. The proof uses the SMV proof assistant, a proof system ba...
- This paper proposes a distributed directory cache coherence protocol and compares the performance of the proposed protocol with fully mapped and single linked list protocols for ...
This paper describes Shasta, a system that supports a shared address space in software on clusters of computers with physically distributed memory. A unique aspect of Shasta compa...
Daniel J. Scales, Kourosh Gharachorloo, Chandramoh...
Run-time parallelization is often the only way to execute the code in parallel when data dependence information is incomplete at compile time. This situation is common in many imp...