Translation caching: skip, don't walk (the page table)

This paper explores the design space of MMU caches that accelerate virtual-to-physical address translation in processor architectures, such as x86-64, that use a radix tree page table. In particular, these caches accelerate the page table walk that occurs after a miss in the Translation Lookaside Buffer. This paper shows that the most effective MMU caches are translation caches, which store partial translations and allow the page walk hardware to skip one or more levels of the page table. In recent years, both AMD and Intel processors have implemented MMU caches. However, their implementations are quite different and represent distinct points in the design space. This paper introduces three new MMU cache structures that round out the design space and directly compares the effectiveness of all five organizations. This comparison shows that two of the newly introduced structures, both of which are translation cache variants, are better than existing structures in many situations. Final...

• Type: Conference
• Year: 2010
• Where: ISCA
• Authors: Thomas W. Barr, Alan L. Cox, Scott Rixner
• Keywords: Hardware, ISCA 2010, Mmu Cache, Page Table, Radix Tree