Drowsy region-based caches: minimizing both dynamic and static power dissipation

Power consumption within the memory hierarchy grows in importance as on-chip data caches occupy increasingly greater die area. Among dynamic power conservation schemes, horizontal partitioning reduces average power per data access by employing multiple smaller structures or using cache subbanks. For instance, region-based caching places small caches dedicated to stack and global accesses next to the L1 data cache. With respect to static power dissipation, leakage power may be addressed at both circuit and architectural levels. Drowsy caches reduce leakage power by keeping inactive lines in a low-power mode. Here we merge drowsy and region-based caching to reduce overall cache power consumption, showing that the combination yields more benefits than either alone. Applications from the MiBench suite exhibit power reductions in the cache system of up to 68-71%, depending on memory configuration, with a small increase in execution time. Categories and Subject Descriptors B.3.2 [Memory Str...

• Type: Conference
• Year: 2005
• Where: CF
• Authors: Michael J. Geiger, Sally A. McKee, Gary S. Tyson
• Keywords: Applied Computing, CF 2005, Data Cache, Leakage Power, Power Consumption