Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis

In high-level synthesis, as for compilers, an important question is when register assignment should take place. Unlike compilers for which the processor architecture is given, synthesizers can, in principle, perform scheduling before register assignment by instantiating, after scheduling, the adequate number of registers (thus with no spilling) and the right connections between operators. However, this approach may sometimes lead to suboptimal data paths. An alternate solution is to let the designer have some control on the compilation process so as to force desirable data paths and resource sharing. For example, in UGH, a public-domain userguided high-level synthesis tool, the designer interacts with the synthesizer by providing an early allocation of scalar variables to registers and a draft data path that describes some or all connections between registers and operators. The well-known drawback of early register assignment is that it over-constrains the scheduler with false depende...

• Type: Conference
• Year: 2007
• Where: ASAP
• Authors: Alain Darte, C. Quinson
• Keywords: ASAP 2007, Data Path, Hardware, Register Assignment, Scheduler first Removes