Scalable Multi-FPGA Platform for Networks-On-Chip Emulation

Interconnect validation is an important early step toward global SoC (System-On-Chip) validation. Fast performances evaluation and design space exploration for NoCs (Networks-On-Chip) are therefore becoming critical issues. A significant speedup of the global validation process for NoC-centric SoCs could be achieved by prototyping such systems on reconfigurable devices (FPGA). However, as SoC complexity increases with the technology scaling, existing general purpose prototyping platforms are far from being suited for large systems. In this paper we present a study for a scalable multi-FPGA platform, designed for NoCs emulation and debugging. This platform allows the integration of complete systems as well as a near cycleaccurate performance estimation.

• Type: Conference
• Year: 2007
• Where: ASAP
• Authors: Abdellah-Medjadji Kouadri-Mostefaoui, Benaoumeur Senouci, Frédéric Pétrot
• Keywords: ASAP 2007, Global Validation Process, Hardware, Important Early Step, SoC Complexity Increases