Address generation for nanowire decoders

Nanoscale crossbars built from nanowires can form high density memories and programmable logic devices. To integrate such nanoscale devices with other circuits, nanowire decoders are needed. Due to the stochastic output of the nanoscale fabrication, the decoder addresses to select the nanowires must be generated after fabrication. In this paper, we develop a mathematical model of the nanowire decoders for the generation of the proper addresses. Assuming a simple testing approach called on-off measurement, we prove that the maximum number of the proper addresses can be generated in finite time. We design the algorithms to generate a required number of the proper addresses. Experimental results confirm the efficiency of our algorithms. Categories and Subject Descriptors: J.6 [Computer-Aided Engineering]: Computer-Aided Design General Terms: Algorithms

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Jia Wang, Ming-Yang Kao, Hai Zhou
• Keywords: GLVLSI 2007, Nanowire, Nanowire Decoders, Proper Addresses, VLSI