A Transient-Resilient System-on-a-Chip Architecture with Support for On-Chip and Off-Chip TMR

The ongoing technological advances in the semiconductor industry make Multi-Processor System-on-a-Chips (MPSoCs) more attractive, because uniprocessor solutions do not scale satisfactorily with increasing transistor counts. In conjunction with the increasing rates of transient faults in logic and memory associated with the continuous reduction of feature sizes, this situation creates the need for novel MPSoC architectures. This paper introduces such an architecture, which supports the integration of multiple, heterogeneous IP cores that are interconnected by a time-triggered Network-on-a-Chip (NoC). Through its inherent fault isolation and determinism, the proposed MPSoC provides the basis for fault tolerance using Triple Modular Redundancy (TMR). On-chip TMR improves the reliability of a MPSoC, e.g., by tolerating a transient fault in one of three replicated IP cores. Off-chip TMR with three MPSoCs can be used in the development of ultra-dependable applications (e.g., X-by-wire), whe...

• Type: Conference
• Year: 2008
• Where: EDCC
• Authors: Roman Obermaisser, Hubert Kraut, Christian El Salloum
• Keywords: Applied Computing, EDCC 2008, IP Cores, Mpsoc Architecture, Transient Fault