Accurate power grid analysis with behavioral transistor network modeling

In this paper, we propose fast and efficient techniques to analyze the power grid with accurate modeling of the transistor network. The solution techniques currently available for power grid analysis rely on a model of representing the transistor network as a current source. The disadvantage of the above model is that the drain capacitance of the PMOS transistors which are already on is not modeled. The drain capacitance of the PMOS transistors which are on, act much like a decoupling capacitance in the power grid. By ignoring the drain capacitance, the voltage drop predicted is pessimistic. This implies that a designer is likely to overestimate the amount of decoupling capacitance needed. In our proposed model, we model the transistor network as a simple switch in series with a RC circuit. The presence of switches leads to a non-constant conductance matrix. So, the switch is modeled behaviorally to make the conductance matrix a constant in presence of switches. The resulting conducta...

• Type: Conference
• Year: 2007
• Where: ISPD
• Authors: Anand Ramalingam, Giri Devarayanadurg, David Z. Pan
• Keywords: Drain Capacitance, Hardware, ISPD 2007, Power Grid, Transistor Network