Hybrid Error-Detection Approach with No Detection Latency for High-Performance Microprocessors

- Error detection plays an important role in fault-tolerant computer systems. Two primary parameters concerned for error detection are the latency and coverage. In this paper, a new, hybrid error-detection approach offering a very high coverage with no detection latency is proposed to protect the data paths of high-performance microprocessors. The feature of no detection latency is essential to real-time error recovery. The hybrid detection approach is to combine the duplication with comparison, triple modular redundancy (TMR) and self-checking mechanisms to construct a formal framework, which allows the error-detection schemes of varying hardware complexity and performance to be incorporated. We develop three error-detection schemes using the concept of hybrid approach to demonstrate the design compromise among the hardware overhead, performance degradation and error-detection coverage (EDC). Three detection schemes are then implemented in an experimental 32-bit VLIW core respectively...

• Type: Conference
• Year: 2006
• Where: CDES
• Authors: Yung-Yuan Chen, Kuen-Long Leu, Li-Wen Lin
• Keywords: CDES 2006, CDES 2007, Detection, Detection Latency, Error Detection