A High Performance, Low Area Overhead Carry Lookahead Adder

Adders are some of the most critical data path circuits requiring considerable design effort in order to "squeeze" out as much performance gain as possible. Many adder designs manage high performance by reducing the delay of the critical path, an effort that results in high area overhead in most cases. In this paper we present a carry lookahead adder (CLA) with a prediction scheme that results in improved performance and low area overhead. Carry prediction enables for the reduction of the carry circuitry within a block while reducing the delay involved in the generation of the carry-out to the subsequent blocks. We have performed simulations of a 16-bit adder and recorded performance improvements of 67% in propagating the carry and generating the sum when compared with the traditional (fixed group4) CLA designed in the same technology. Keywords - carry lookahead, high-performance, adder architecture, carry prediction, area overhead.

• Type: Conference
• Year: 2004
• Where: CSREAESA
• Authors: James Levy, Jabulani Nyathi
• Keywords: Area Overhead, Carry Lookahead, Carry Lookahead Adder, CSREAESA 2004, CSREAESA 2007