Switching Activity Minimization in Combinational Logic Design

: In this paper we focus on the reduction of switching activity in combinational logic circuits. An algorithmic approach using k-map has been proposed which modifies the normal optimal solution obtained from k-map to reduce its switching activity. More than 10% reduction in switching activity has been observed using our method. The final solution gives a good trade off between cost and power consumption.

• Type: Conference
• Year: 2004
• Where: CSREAESA
• Authors: R. V. Menon, S. Chennupati, Naveen K. Samala, Damu Radhakrishnan, Baback A. Izadi
• Keywords: Combinational Logic Circuits, CSREAESA 2004, CSREAESA 2007, Normal Optimal Solution, Switching Activity