Balance Testing of Logic Circuits

We present a new test response compression method called cumulative balance testing (CBT)that extends both balance testing and accumulatorcompression testing. CBT uses an accumulated balance signature,and it guaranteesvery high error coverage (over 99%)for various error models. We demonstrate that the single stuck-line (SSL) fault coverage of CBT for many of the ISCAS85 combinational benchmark circuitsis loo%,and for all but one circuit, the fault coverage is over 99.5%. To make processor circuits self-testing, any existing accumulators and counters can be exploited to implement CBT. Its ease of implementation,provably high error coverage,and exceptionally high SSL fault coverage,even with reduced (nonexhaustive)test sets, make CBT suitable for the built-in self testing of processor circuits that require a guaranteed level of test confidence.

• Type: Conference
• Year: 1993
• Where: FTCS
• Authors: Krishnendu Chakrabarty, John P. Hayes
• Keywords: Balance Testing, Cumulative Balance Testing, Fault Coverage, FTCS 1993