A Hardware Implementation of the Advanced Encryption Standard (AES) Algorithm using SystemVerilog

In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consumed during different iterations of encryption, are generated in parallel with the encryption process. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintext block. This leads to an increase in the message encryption throughput. The proposed pipelined design was modeled and validated in SystemVerilog hardware description language. The pipelined design was synthesized using the Synopsys Design Compiler tool and LSI_10K technology library. The synthesized gate-level netlist can operate at 40MHz frequency. To get an estimate of the speed gain by the hardware implementation, a virtual system was created using the Virtutech

• Type: Conference
• Year: 2010
• Where: CATA
• Authors: Bahram Hakhamaneshi, Behnam S. Arad
• Keywords: CATA 2007, CATA 2010, Computer Science, Encryption, Hardware Implementation, Overall Encryption Delay