Optimization of Area and Delay at Gate-Level in Multiple Constant Multiplications

—Although many efficient high-level algorithms have been proposed for the realization of Multiple Constant Multiplications (MCM) using the fewest number of addition and subtraction operations, they do not consider the low-level implementation issues that directly affect the area, delay, and power dissipation of the MCM design. In this paper, we initially present area efficient addition and subtraction architectures used in the design of the MCM operation. Then, we propose an algorithm that searches an MCM design with the smallest area taking into account the cost of each operation at gatelevel. To address the area and delay tradeoff in MCM design, the proposed algorithm is improved to find the smallest area solution under a delay constraint. The experimental results show that the proposed algorithms yield low-complexity and high-speed MCM designs with respect to those obtained by the prominent algorithms designed for the optimization of the number of operations and the optimizatio...

• Type: Conference
• Year: 2010
• Where: DSD
• Authors: Levent Aksoy, Eduardo Costa, Paulo F. Flores, José C. Monteiro
• Keywords: Algorithms, Constant Multiplications, DSD 2010, Hardware, MCM Design