Custom parallel caching schemes for hardware-accelerated image compression

Abstract In an effort to achieve lower bandwidth requirements, video compression algorithms have become increasingly complex. Consequently, the deployment of these algorithms on Field Programmable Gate Arrays (FPGAs) is becoming increasingly desirable, because of the computational parallelism on these platforms as well as the measure of flexibility afforded to designers. Typically, video data is stored in large and slow external memory arrays, but the impact of the memory access bottleneck may be reduced by buffering frequently used data in fast on-chip memories. The order of the memory accesses, resulting from many compression algorithms are dependent on the input data [18]. These data dependent memory accesses complicate the exploitation of data re-use, and subsequently reduce the extent to which an application may be accelerated. In this paper, we present a hybrid memory sub-system which is able to capture data re-use effectively in spite of data dependent memory accesses. This memo...

• Type: Journal
• Year: 2008
• Where: JRTIP
• Authors: Su-Shin Ang, George A. Constantinides, Wayne Luk, Peter Y. K. Cheung
• Keywords: Compression Algorithms, JRTIP 2008, Memory Sub-system, Slow External Memory