Low-overhead checkpointing and rollback is a popular technique for fault recovery. While different approaches are possible, hardware-supported checkpointing and rollback at the cache level is especially interesting. The main reason is that the microarchitecture required can be easily integrated and used effectively in modern processor microarchitectures. Unfortunately, proposed cache-level checkpointing schemes provide little implementation information and do not support a large rollback window all the time. In this paper, we outline the design of SWICH, a new cache-level checkpointing scheme that, while being efficiently implemented in modern processors, supports a large rollback window continuously. This is accomplished by relying on two live checkpoints at all times to form a sliding rollback window. We build an FPGA-based prototype of SWICH. The evaluation of the prototype shows that a simple processor can support the sliding window with little additional logic and memory hardware...