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IEICET
2007

An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits

14 years 12 days ago
An Inhibitory Neural-Network Circuit Exhibiting Noise Shaping with Subthreshold MOS Neuron Circuits
We designed subthreshold analog MOS circuits implementing an inhibitory network model that performs noise-shaping pulse-density modulation with noisy neural elements. Our aim is to develop a possible ultralow-power delta-sigma-type one-bit analog-to-digital converter. Through circuit simulations we confirmed that the signal-to-noise ratio of the network was improved by 7.9 dB compared with that of the uncoupled one as a result of noise shaping.
Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshi
Added 14 Dec 2010
Updated 14 Dec 2010
Type Journal
Year 2007
Where IEICET
Authors Akira Utagawa, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
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