Sciweavers

JSA
2007

Asynchronous arbiter for micro-threaded chip multiprocessors

13 years 10 months ago
Asynchronous arbiter for micro-threaded chip multiprocessors
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors (CMP) and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk) provided by the micro-threaded microprocessor model to set the priority processor and move the circulated arbitration token at the most likely processor to issue the create instruction. This mechanism provides latency hiding during token circulation by decoupling the microthreaded processor from the ring’s timing. The arbiter provides a very simple arbitration mechanism and can be used for chip multiprocessor arbitration purposes.
Nabil Hasasneh, Ian Bell, Chris R. Jesshope
Added 16 Dec 2010
Updated 16 Dec 2010
Type Journal
Year 2007
Where JSA
Authors Nabil Hasasneh, Ian Bell, Chris R. Jesshope
Comments (0)