DVFS in loop accelerators using BLADES

Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-to-market and reduced non-recurring engineering costs, automatic systems that can rapidly generate hardware bearing both power and performance in mind are extremely attractive. This paper proposes the BLADES (Better-than-worst-case Loop Accelerator Design) system for automatically designing self-tuning hardware accelerators that dynamically select their best operating frequency and voltage based on environmental conditions, silicon variation, and input data characteristics. Errors in operation are detected by Razor flip-flops, and recovery is initiated. The architecture efficiently supports detection, rollback, and recovery to provide a highly adaptable and configurable loop accelerator. The overhead of deploying Razor flip-flops is significantly reduced by automatically chaining primitive computation operatio...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott A. Mahlke, David Bull
• Keywords: Configurable Loop Accelerator, DAC 2008, Design Automation, Nominal Supply Voltage, Self-tuning Hardware Accelerators