An energy optimization is proposed that addresses the nontrivial digital contribution to power and impact on performance in high-speed mixed-signal circuits. Parallel energy and behavioral models are used to quantify architectural tradeoffs across the analog/digital boundary. An interleaved ADC is optimized as a case study to demonstrate this approach. The chosen operating point of 36 channels and 700mV operation gives a 3? improvement in energy compared to the seed of the model. The model matches closely the measured results of an ADC testchip implemented in a 65nm CMOS process. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids General Terms Design, Theory Keywords Mixed-signal circuits, Optimization, Analog-to-digital converters, Low-power
Brian P. Ginsburg, Anantha P. Chandrakasan