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    FPGA area reduction by multi-output function based sequential resynthesis

    15 years 13 days ago
    FPGA area reduction by multi-output function based sequential resynthesis
    Download  www.ee.ucla.edu
    Yu Hu, Victor Shih, Rupak Majumdar, Lei He
    claim paper
    Added 12 Nov 2009
    Updated 12 Nov 2009
    Type Conference
    Year 2008
    Where DAC
    Authors Yu Hu, Victor Shih, Rupak Majumdar, Lei He
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