On the role of timing masking in reliable logic circuit design

Soft errors, once only of concern in memories, are beginning to affect logic as well. Determining the soft error rate (SER) of a combinational circuit involves three main masking mechanisms: logic, timing and electrical. Most previous papers focus on logic and electrical masking. In this paper we develop static and statistical analysis techniques for timing masking that estimate the error-latching window of each gate. Our SER evaluation algorithms incorporating timing masking are orders of magnitude faster than comparable evaluators and can be used in synthesis and layout. We show that 62% of gates identified as error-critical using timing masking would not be identifiable by considering only logic masking. Furthermore, hardening the top 10% of errorcritical gates leads to a 43% reduction in the SER. We also propose a more subtle solution, gate-relocation for technologies where wire delay dominates gate delay. We decrease the error-latching window of each gate by relocating it in such...

• Type: Conference
• Year: 2008
• Where: DAC
• Authors: Smita Krishnaswamy, Igor L. Markov, John P. Hayes
• Keywords: DAC 2008, Design Automation, Electrical Masking, Logic Masking, Main Masking Mechanisms