Code Compression for Embedded Systems

Memory is one of the most restricted resources in many modern embedded systems. Code compression can provide substantial savings in terms of size. In a compressed code CPU, a cache miss triggers the decompression of a main memory block, before it gets transferred to the cache. Because the code must be decompressible starting from any point or at least at cache block boundaries, most le-oriented compression techniques cannot be used. We propose two algorithms to compress code in a space-e cient and simple to decompress way, one which is independent of the instruction set and another which depends on the instruction set. We perform experiments on two instruction sets, a typical RISC MIPS and a typical CISC x86 and compare our results to existing le-oriented compression algorithms.

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Haris Lekatsas, Wayne Wolf
• Keywords: Cache Block Boundaries, Cache Miss Triggers, Compressed Code Cpu, DAC 1998, Design Automation