Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce

This paper presents a method for power and ground (p/g) network routing for high speed CMOS chips with multiple p/g pads. Our objective is not to reduce the total amount of the ground bounce, but to distribute it more evenly among the pads while the routing area is kept to a minimum. We first show that proper p/g terminal to pad assignment is necessary to reduce the maximum ground bounce and then present a heuristic for performing simultaneous assignment and p/g net routing. Experimental results demonstrate the effectiveness of our method.

• Type: Conference
• Year: 1998
• Where: DAC
• Authors: Jaewon Oh, Massoud Pedram
• Keywords: DAC 1998, Design Automation, Maximum Ground Bounce, Simultaneous Assignment, Speed Cmos Chips