Exploiting multiple switch libraries in topology synthesis of on-chip interconnection network

Abstract—On-chip interconnection network is a crucial design component in high-performance System-on-Chips (SoCs). Many of previous works have focused on the automation of its topology design, since the topology largely determines its overall performance. For this purpose, they mostly require a switch library which includes all possible switch configurations (e.g. the number of in/output ports and data width) with their implementation costs such as delay, area, and power. More precisely, they characterize the switches by synthesizing them with a common design objective (e.g. minimizing area) and common design constraints for a given gate-level design library. The implementation costs are used in evaluating the topologies throughout the topology synthesis. The major drawback of single switch library approach is that it forces the topology synthesis methods to search the best topology with the assumption that all the switches comprising a topology will be implemented (synthesized) wit...

• Type: Journal
• Year: 2010
• Where: DATE
• Authors: Minje Jun, Sungroh Yoon, Eui-Young Chung
• Keywords: Common Design, DATE 2010, Design, Hardware, Topology