The design and use of simplepower: a cycle-accurate energy estimation tool

In this paper, we presen t the design and use of a comprehensiv e framework, SimplePower, for evaluating the e ect of high-level algorithmic, architectural, and compilation tradeo s on energy. An execution-driven, cycle-accurate RT lev el energy estimation tool that uses transition sensitive energy models forms the cornerstone of this framework. SimplePower also provides the energy consumed in the memory system and on-chip buses using analytical energy models. We presen t the use ofSimplePower to evaluate the impact of a new selective gated pipeline register optimization, a high-level data transformation and a pow er-conscious post compilation optimization register relabeling on the datapath, memory and on-chip bus energy, respectiv ely.We nd that these three optimizations reduce the energy by 18-36 in the datapath, 62 in the memory system and 12 in the instruction cache data bus, respectively.

• Type: Conference
• Year: 2000
• Where: DAC
• Authors: Wu Ye, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin
• Keywords: DAC 2000, Design Automation, Lev El Energy, On-chip Bus Energy, Sensitive Energy Models