Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores

Crosstalk effects degrade the integrity of signals traveling on long interconnects and must be addressed during manufacturing testing. External testing for crosstalk is expensive due to the need for high-speed testers. Built-in self-test, while eliminating the need for a high-speed tester, may lead to excessive test overhead as well as overly aggressive testing. To address this problem, we propose a new software-based self-test methodology for systemon-chips (SoC) based on embedded processors. It enables an onchip embedded processor core to test for crosstalk in system-level interconnects by executing a self-test program in the normal operational mode of the SoC. We have demonstrated the feasibility of this method by applying it to test the interconnects of a processor-memory system. The defect coverage was evaluated using a system-level crosstalk defect simulation method.

• Type: Conference
• Year: 2001
• Where: DAC
• Authors: Li Chen, Xiaoliang Bai, Sujit Dey
• Keywords: DAC 2001, Design Automation, Software-based Self-test Methodology, System-level Crosstalk Defect, System-level Interconnects