A solenoidal basis method for efficient inductance extraction

The ability to compute the parasitic inductance of the interconnect is critical to the timing verification of modern VLSI circuits. A challenging aspect of inductance extraction is the solution of large, dense, complex linear systems of equations via iterative methods. Accelerating the convergence of the iterative method through preconditioning is made difficult due to the non-availability of the system matrix. This paper presents a novel algorithm to solve these linear systems by restricting current to a discrete solenoidal subspace in which Kirchoff's law is obeyed, and solving a reduced system via an iterative method such as GMRES. A preconditioner based on the Green's function is used to achieve near-optimal convergence rates in several cases. Experiments on a number of benchmark problems illustrate the advantages of the proposed method over FastHenry. Categories and Subject Descriptors B.7.2 [Integrating Circuits]: Design Aids--placement and routing, simulation, verific...

• Type: Conference
• Year: 2002
• Where: DAC
• Authors: Hemant Mahawar, Vivek Sarin, Weiping Shi
• Keywords: DAC 2002, Design Automation, Iterative Method, Iterative Methods, Keywords Inductance Extraction