Post-layout logic optimization of domino circuits

Logic duplication, a commonly used synthesis technique to remove trapped inverters in reconvergent paths of Domino circuits, incurs high area and power penalties. In this paper, we propose a synthesis scheme to reduce the duplication cost by allowing inverters in Domino logic under certain timing constraints. In order to guarantee the robustness of such Domino circuits, we perform the reduction of logic duplication at the physical level. Experimental results show significant reduction in duplication cost, which translates into significant improvements in area, power, and/or delay. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids--Automatic synthesis, Optimization; B.7.2 [Integrated Circuits]: Design Aids-Layout General Terms Algorithms Keywords Domino logic, synthesis, optimization, layout

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Aiqun Cao, Cheng-Kok Koh
• Keywords: DAC 2004, Design Automation, Domino Circuits, Domino Logic, Logic Duplication