Statistical optimization of leakage power considering process variations using dual-Vth and sizing

timing analysis tools to replace standard deterministic static timing analyzers whereas [8,27] develop approaches for the statistical estimation of leakage power considering within-die and across-die variations. Increasing levels of process variability in sub-100nm CMOS design has become a critical concern for performance and power constraint designs. In this paper, we propose a new statistically aware Dual-Vt and sizing optimization that considers both the variability in performance and leakage of a design. While extensive work has been performed in the past on statistical analysis methods, circuit optimization is still largely performed using deterministic methods. We show in this paper that deterministic optimization quickly looses effectiveness for stringent performance and leakage constraints in designs with significant variability. We then propose a statistically aware dual-Vt and sizing algorithm where both delay constraints and sensitivity computations are performed in a statis...

• Type: Conference
• Year: 2004
• Where: DAC
• Authors: Ashish Srivastava, Dennis Sylvester, David Blaauw
• Keywords: DAC 2004, Design Automation, Deterministic Optimization, Deterministic Static Timing, Statistical Optimization