Low Latency Recovery from Transient Faults for Pipelined Processor Architectures

Abstract--Recent technology trends have made radiationinduced soft errors a growing threat to the reliability of microprocessors, a problem previously only known to the aerospace industry. Therefore, the ability to handle higher soft error rates in modern processor architectures is essential in order to allow further technology scaling. This paper presents an efficient fault-tolerance method for pipeline-based processors using temporal redundancy. Instructions are executed twice at each pipeline stage, which allows the detection of transient faults. Once a fault is detected the execution is stopped immediately and recovery is implicitly performed within the pipeline stages. Due to this fast reaction the fault is contained at its origin and no expensive rollback operation is required later on.

• Type: Journal
• Year: 2010
• Where: DSD
• Authors: Marcus Jeitler, Jakob Lechner
• Keywords: DSD 2010, Efficient Fault-tolerance Method, Hardware, Modern Processor Architectures, Soft Error