Persistent CAD for in-the-field Power Optimization

A major focus within the Integrated Chip (IC) industry is reducing power consumption of devices. In this paper, we explore the idea of persistent CAD algorithms that constantly improve the power consumption of consumer devices that use FPGAs. The idea is that the field-programmability of an FPGA allows updates to be deployed in the field, and as CAD algorithms find optimizations for a design, these optimizations can be deployed into the field. To explore this idea, we have created a persistent placement algorithm for FPGAs using a genetic algorithm. We describe the design of this genetic algorithm, and then use it in an experiment to show the impact on power consumption. Our results for one of the larger MCNC benchmarks, clma, shows that over a 60 minute period better placement solutions are found, but the rate at which these solutions are found decreases quickly.

• Type: Journal
• Year: 2010
• Where: ERSA
• Authors: Peter Jamieson
• Keywords: Algorithm, ERSA 2010, Genetic Algorithm, Hardware, Power Consumption