FPGA-based combined architecture for stream categorization and intrusion detection

This paper presents a working solution for the MEMOCODE 2010 design contest. The design presented in this paper is implemented in the Xilinx V5LX330 FPGA as a custom circuit. The solution implements pattern matching logic for all the mandatory and optional patterns while maintaining the required line rate of 500 Mbps. Keywords-DFA; pattern matching; FPGA

• Type: Journal
• Year: 2010
• Where: MEMOCODE
• Authors: Sunil Shukla, Rodric Rabbah, Martin Vorbach
• Keywords: Formal Methods, MEMOCODE 2010, MEMOCODE 2010 Design, Required Line Rate, Xilinx V5LX330 FPGA