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JISE
2011

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Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits

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Design Planning with 3D-Via Optimization in Alternative Stacking Integrated Circuits

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Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

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Added	14 May 2011
Updated	14 May 2011
Type	Journal
Year	2011
Where	JISE
Authors	Chao-Hung Lu, Hung-Ming Chen, Chien-Nan Jimmy Liu

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