Subthreshold logical effort: a systematic framework for optimal subthreshold device sizing

Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold regime are significantly different from those in strong-inversion. This presents new challenges in design optimization, particularly in complex gates with stacks of transistors. In this paper, we demonstrate a new optimal sizing scheme for subthreshold designs which takes these issues into account. We derive a closed-form solution for the correct sizing of transistors in a stack, both in relation to other transistors in the stack, and to a single transistor with equivalent current drivability. Experimental results show that our framework provides a performance improvement of up to 13.5% over the conventional logical effort method on ISCAS benchmark circuits, while one component circuit demonstrated an improvement of 33.1%. Categories and Subject Descriptors B.7.2 [Hardware]: Integrated Circ...

• Type: Conference
• Year: 2006
• Where: DAC
• Authors: John Keane, Hanyong Eom, Tae-Hyoung Kim, Sachin S. Sapatnekar, Chris H. Kim
• Keywords: Conventional Logical Effort, DAC 2006, Design Automation, MOS Transistors, Optimal Sizing Scheme