Sciweavers

Free Online Productivity Tools i2Speak i2Symbol i2OCR iTex2Img iWeb2Print iWeb2Shot i2Type iPdf2Split iPdf2Merge i2Bopomofo i2Arabic i2Style i2Image i2PDF iLatex2Rtf Sci2ools

17

MAM
2010

favoriteEmaildiscussreport

121views Communications» more MAM 2010»

A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

13 years 5 months ago

A high performance ECC hardware implementation with instruction-level parallelism over GF(2163)

Download homepage.usask.ca

Yu Zhang, Dongdong Chen, Younhee Choi, Li Chen, Se

Real-time Traffic

Communications | MAM 2010 |

claim paper

Related Content

» Superscalar Coprocessor for HighSpeed CurveBased Cryptography

» Ultra High Performance ECC over NIST Primes on Commercial FPGAs

» Instruction Level Parallelism through Microthreading A Scalable Approach to Chip Multipro...

» XTR Implementation on Reconfigurable Hardware

» A PublicKey Cryptographic Processor for RSA and ECC

» A High Throughput FPGABased Implementation of the Lanczos Method for the Symmetric Extrema...

» An Architecture Framework for Introducing Predicated Execution into Embedded Microprocesso...

» Hardwaresoftware codesign architecture for thermal management of chip multiprocessors

» Multiobjective Optimization of a Parameterized VLIW Architecture

Post Info
More Details (n/a)

Added	20 May 2011
Updated	20 May 2011
Type	Journal
Year	2010
Where	MAM
Authors	Yu Zhang, Dongdong Chen, Younhee Choi, Li Chen, Seok-Bum Ko

Comments (0)