A Low-Power DSP for Wireless Communications

This paper proposes a low-power high-throughput digital signal processor (DSP) for baseband processing in wireless terminals. It builds on our earlier architecture--Signal processing On Demand Architecture (SODA)--which is a four-processor, 32-lane SIMD machine that was optimized for WCDMA 2 Mbps and IEEE 802.11a. SODA has several shortcomings including large register file power, wasted cycles for data alignment, etc., and cannot satisfy the higher throughput and lower power requirements of emerging standards. We propose SODA-II, which addresses these problems by deploying the following schemes: operation chaining, pipelined execution of SIMD units, staggered memory access, and multicycling of computation units. Operation chaining involves chaining the primitive instructions, thereby eliminating unnecessary register file accesses and saving power. Pipelined execution of the vector instructions through the SIMD units improves the system throughput. Staggered execution of computation uni...

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Hyunseok Lee, Chaitali Chakrabarti, Trevor N. Mudge
• Keywords: Architecture, Artificial Intelligence, Computation Units, SIMD Units, TVLSI 2010