Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks

Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's attention due to its appealing tradeoff between variation tolerance and power overhead. In this work, we investigate how to optimize such clock networks through buffer and wire sizing. A two-stage hybrid optimization approach is proposed. It considers the realistic constraint of discrete buffer/wire sizes and is based on accurate delay models. In order to provide reliable and efficient guidance for the optimization, we suggest to apply SVM (Support Vector Machine) based machine learning as a surrogate for expensive circuit-level simulation. Experimental results on benchmark circuits show that our sizing method can reduce clock skew by 43% on average with very small increase on power dissipation. Categories and Subject Descriptors B.6.3 [Logic Design]: Design Aids- Optimization; J.6 [Computeraided Engineering...

• Type: Journal
• Year: 2010
• Where: TVLSI
• Authors: Rupak Samanta, Jiang Hu, Peng Li
• Keywords: Artificial Intelligence, Clock Networks, Link-based Non-tree Clock, TVLSI 2010, Two-stage Hybrid Optimization