On error modeling of electrical bugs for post-silicon timing validation

—There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timing validation. In this paper, we show the inadequacy of existing methods (due to either inaccuracy or a lack of scalability) and propose an approach that leverages debug engineers’ experience to model timing errors efficiently and with sufficient precision. Experimental results demonstrate that the proposed approach produced an error model six times more accurate than the prior art with a negligible simulation overhead.

• Type: Journal
• Year: 2012
• Where: ASPDAC
• Authors: Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing-Jia Liou
• Keywords: ASPDAC 2012, Error Model, Hardware, Inadequacy, Prior Art