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    ASPDAC
    2012
    ACM
    279views Hardware» more  ASPDAC 2012»
    Block-level 3D IC design with through-silicon-via planning
    12 years 6 months ago
    Block-level 3D IC design with through-silicon-via planning
    Download  www.gtcad.gatech.edu
    — Since re-designing and re-optimizing existing logic, memory, and IP blocks in a 3D fashion significantly increases design cost, nearterm three-dimensional integrated circuit (...
    Dae Hyun Kim, Rasit Onur Topaloglu, Sung Kyu Lim
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    ASPDAC
    2012
    ACM
    334views Hardware» more  ASPDAC 2012»
    GreenDroid: An architecture for the Dark Silicon Age
    12 years 6 months ago
    GreenDroid: An architecture for the Dark Silicon Age
    Download  cseweb.ucsd.edu
    — The Dark Silicon Age kicked off with the transition to multicore and will be characterized by a wild chase for seemingly ever-more insane architectural designs. At the heart o...
    Nathan Goulding-Hotta, Jack Sampson, Qiaoshi Zheng...
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    ASPDAC
    2012
    ACM
    241views Hardware» more  ASPDAC 2012»
    Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
    12 years 6 months ago
    Post-fabrication reconfiguration for power-optimized tuning of optically connected multi-core systems
    Download  cadlab.ece.ucsb.edu
    Abstract— Integrating optical interconnects into the nextgeneration multi-/many-core architecture has been considered a viable solution to addressing the limitations in throughpu...
    Yan Zheng, Peter Lisherness, Saeed Shamshiri, Amir...
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    ASPDAC
    2012
    ACM
    281views Hardware» more  ASPDAC 2012»
    Abstract system-level models for early performance and power exploration
    12 years 6 months ago
    Abstract system-level models for early performance and power exploration
    Download  users.ece.utexas.edu
    Andreas Gerstlauer, Suhas Chakravarty, Manan Kathu...
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    ASPDAC
    2012
    ACM
    253views Hardware» more  ASPDAC 2012»
    An integrated and automated memory optimization flow for FPGA behavioral synthesis
    12 years 6 months ago
    An integrated and automated memory optimization flow for FPGA behavioral synthesis
    Download  cadlab.cs.ucla.edu
    Behavioral synthesis tools have made significant progress in compiling high-level programs into register-transfer level (RTL) specifications. But manually rewriting code is still ...
    Yuxin Wang, Peng Zhang, Xu Cheng, Jason Cong
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    ASPDAC
    2012
    ACM
    290views Hardware» more  ASPDAC 2012»
    CODA: A concurrent online delay measurement architecture for critical paths
    12 years 6 months ago
    CODA: A concurrent online delay measurement architecture for critical paths
    Download  www.cse.cuhk.edu.hk
    With technology scaling, integrated circuits behave more unpredictably due to process variation, environmental changes and aging effects. Various variation-aware and adaptive desi...
    Yubin Zhang, Haile Yu, Qiang Xu
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    ASPDAC
    2012
    ACM
    241views Hardware» more  ASPDAC 2012»
    On error modeling of electrical bugs for post-silicon timing validation
    12 years 6 months ago
    On error modeling of electrical bugs for post-silicon timing validation
    Download  cadlab.ece.ucsb.edu
    —There is great demand for an accurate and scalable metric to evaluate the functional stimuli, testbench checkers, and DfD (Design-for-Debug) structures used in post-silicon timi...
    Ming Gao, Peter Lisherness, Kwang-Ting Cheng, Jing...
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    ASPDAC
    2012
    ACM
    265views Hardware» more  ASPDAC 2012»
    Improving validation coverage metrics to account for limited observability
    12 years 6 months ago
    Improving validation coverage metrics to account for limited observability
    Download  cadlab.ece.ucsb.edu
    —In both pre-silicon and post-silicon validation, the detection of design errors requires both stimulus capable of activating the errors and checkers capable of detecting the beh...
    Peter Lisherness, Kwang-Ting Cheng
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    ASPDAC
    2012
    ACM
    247views Hardware» more  ASPDAC 2012»
    Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
    12 years 6 months ago
    Through-silicon-via-induced obstacle-aware clock tree synthesis for 3D ICs
    Download  www.gtcad.gatech.edu
    — In this paper, we present an obstacle-aware clock tree synthesis method for through-silicon-via (TSV)-based 3D ICs. A unique aspect of this problem lies in the fact that variou...
    Xin Zhao, Sung Kyu Lim
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    ASPDAC
    2012
    ACM
    265views Hardware» more  ASPDAC 2012»
    GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
    12 years 6 months ago
    GLOW: A global router for low-power thermal-reliable interconnect synthesis using photonic wavelength multiplexing
    Download  www.cerc.utexas.edu
    In this paper, we examine the integration potential and explore the design space of low power thermal reliable on-chip interconnect synthesis featuring nanophotonics Wavelength Di...
    Duo Ding, Bei Yu, David Z. Pan
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