Controllability-driven Power Virus Generation for Digital Circuits

The problem of peak power estimation in CMOS circuits is essential for analyzing the reliability and performance of circuits at extreme conditions. The Power Virus problem involves finding input vectors that cause maximum dynamic power dissipation (maximum toggles) in circuits. In this paper, an approach for power virus generation for both combinational and sequential circuits is presented. The basic intuition behind the approach is to use the 0- and 1- controllability measures of the gate outputs in the circuit to guide the D-Algorithm. The proposed technique was employed on the ISCAS'85 and ISCAS'89 circuits. The results of the above show a significant increase in power dissipation when compared to the best known existing techniques reported in the literature. Keywords? CMOS circuits, Power dissipation, Power virus, Automatic Test Pattern Generation, Fanout Free Regions.

• Type: Conference
• Year: 2007
• Where: VLSID
• Authors: K. Najeeb, Karthik Gururaj, V. Kamakoti, Vivekananda M. Vedula
• Keywords: Computer Architecture, Dynamic Power Dissipation, Power Virus Generation, Power Virus Problem, VLSID 2007