A low power multilevel interconnect architecture that uses wave-pipelined multiplexed (WPM) interconnect routing is proposed in this paper. WPM takes advantage of existing interconnect idleness and implements lowoverhead wire sharing to reduce the number of routing tracks required for intra-macrocell communication. It is shown that the extra available routing area could then be used to redesign the interconnect network to substantially reduce coupling capacitance and driver sizes. System-level simulation reveals that the systematic application of WPM reduces total power of a 40M transistor macrocell by almost 28% without any loss in performance.
Ajay Joshi, Vinita V. Deodhar, Jeffrey A. Davis