On the Implementation of a Low-Power IEEE 802.11a Compliant Viterbi Decoder

This article describes a standard cell based novel implementation of a low-power Viterbi Decoder (VD) targeted for the IEEE 802.11a Wireless LAN system. Multiple clock rates have been used to reduce the power consumption and the inherent bandwidth mismatch between the Add-Compare-Select (ACS) and traceback operations. Aggressive clock gating and innovative circuit techniques reduce the power consumption further. The normalized cell area and dynamic power consumption of the designed VD are 5.9 mm 2 and 53 mW respectively. The normalized power dissipation of the VD is 0.66 mW / Mbps.

• Type: Conference
• Year: 2006
• Where: VLSID
• Authors: Koushik Maharatna, Alfonso Troya, Milos Krstic, Eckhard Grass
• Keywords: Computer Architecture, Dynamic Power Consumption, Normalized Cell Area, Normalized Power Dissipation, VLSID 2006